The present invention relates to a semiconductor memory device, and particularly to technology that can be effectively adapted to a semiconductor memory device having memory cells comprised of series circuits of switching elements and data-storing capacitor elements
A semiconductor integrated circuit device (hereinafter referred to as DRAM) equipped with a dynamic random access memory has been used as a semiconductor integrated circuit device having a memory function capable of rewriting the data. A memory cell of one bit of DRAM is simply constituted by a series circuit of an element for switching (selecting memory cell) and an capacitor element for storing the data This makes it possible to reduce the areas occupied by the memory cells and to increase the storing capacity
As the degree of integration increases, however, it becomes difficult to maintain sufficient areas for the memory cells and, particularly, to maintain sufficient areas for the capacitors. As can be appreciated, decrease in the area for the capacitors results in a decrease of the amount of stored electric charge that serves as data. This decreased amount of stored electric charge becomes a cause of erroneous operation at the time of reading the data, and of soft errors that stem from o particles. In order to increase the amount of electric charge that serves as data and that is to be stored, attempts have been made to employ technology to constitute capacitors by utilizing moats or trenches that help increase means for storing the charge (e.g., Japanese Patent Publication No. 12739/1983). The inventors, however, have discovered a problem that the existing photolithography is not capable of forming the moats or trenches maintaining a uniform shape or depth, thus making it difficult to mass-produce DRAM's in a highly integrated form.
Further, the memory cells must be electrically isolated from a plurality of neighboring memory cells in a memory cell array. The memory cells are isolated by a field insulating film that is formed by oxidizing a semiconductor substrate using an oxidation impermeable mask. With this isolation technique, the semiconductor substrate under the oxidation impermeable mask is also oxidized to some extent, so that the difference increases between the size of the oxidation impermeable mask and the size of the field insulating film. That is, the area of the field insulating film increases while the areas of the memory cells decrease, and particularly the areas of the capacitors decrease. It was thus found that the storage of electric charge that serves as data decreases, the device erroneously operates at the time of reading the data, and soft error develops due to .alpha. particles, making it difficult to form the DRAM in a highly integrated form or to have an increased storage of electric charge.
A technique for preventing error in the amount of dimensional conversion in the above-mentioned isolation technique has been disclosed, for example, in Japanese Patent Laid-Open No. 188866/1982.